The present invention relates generally to chip design, and more specifically, to control path power adjustment for chip design.
After determination of an initial layout of a chip, for example, a system on a chip (SOC), during the design phase, power reduction processing may be performed on the chip layout in order to reduce the overall power consumed by the chip. Various power reduction techniques may be applied to a chip design. Power reduction processing may also be referred to as power down processing, and may be performed by changing various components of a chip design (for example, standard cells or devices) in order to achieve additional power savings without hurting chip performance. For example, the assigned drive strength and threshold voltage of a chip component in the initial chip layout may be more than is required to meet the performance targets of the chip; therefore, the chip component may be replaced with a lower drive strength or slower threshold voltage device by the power down processing. Power down processing may be performed by parsing a data structure, such as a netlist, of the chip design and evaluating power down suitability of each component in the chip design. The netlist is a data structure that describes the topology of an electronic design by listing all components of the device, including of all the component terminals, and the various electrical connections between the various component terminals.